A number of different tests may be commonly performed to validate or test advanced integrated circuits (ICs). For example, a SCAN TEST scans an IC based on known input and expected output strings. An IDDQ test measures the quiescent current on a power pin (such as VDD) to check for current leaks or shorts within an IC device.
The most rigorous testing, however, and generally the most difficult to perform, is commonly referred to as “functional” testing. Ideally, a functional test runs the device at rated speed and ensures that the device works as intended (e.g. provides “at speed” the expected outputs). For advanced ICs, a “functional test” generally requires advanced automated test equipment (ATE).
An alternative mechanism for performing a type of functional test is to perform a LOOP TEST e.g. by connecting the transmit and receive pins. However, this method is not as good as a true functional test because a defect in one pin may be masked by an enhanced performance by another pin.
A variety of ATE equipment is known in the art. Generally such equipment is able to drive the input of up to all input pins and sample the output of up to all output pins. This can be particularly challenging for high speed chips (such as IC with data inputs and/or outputs operating at up to about 770 MHz) because it can be a challenge for an ATE to keep up with the operating speeds of an IC under test.
Some types of Automated Test Equipment (ATE) used in digital IC functional testing provides either a pass or a fail result for an output pin up to each output pin based on a sample taken from an output pin of a Device Under Test (DUT) at a fixed time (sometimes referred to as a strobe). The pass or fail result for an output pin is typically based on comparing the output of the output to a pattern of expected outputs, which is commonly stored in some types of ATEs in a pattern memory. Test results are commonly captured in some types of ATEs in a capture memory.
As will be understood in the art, a DUT can include any type of information or digital or signal processing device, including but not limited to a packaged integrated circuit, a device on a wafer probed before packaging, a system comprising multiple circuits or ICs, etc. A pin may refer to a pin on a packaged IC, a pad on a wafer, or an output pin on an information or communication system.
Some types of ATE systems have a pattern memory (often a separate memory or memory area for each pin under test (PUT)) and a capture memory for each pin. At the appropriate start time, the ATE compares the output of the DUT with the pattern in the pattern memory and can store results of such a compare in the capture memory. Thus, the capture memory will indicate whether any test failed on a pin and may indicate which test failed or precisely when the test failed.
An implicit requirement of this type of testing is that the DUT output logic states are deterministic and repeatable in time over the small fluctuations in the otherwise tightly controlled operating conditions and manufacturing variations. Unfortunately, this model of the DUT fails to apply when the period of the output data is very small. With increased output operating frequency, the time that the expected data sequence reaches the tester pins (e.g. the delay of the data in reaching the pins) varies so much in relation to the period that setting a fixed time within the cycle to strobe the outputs is not possible. Consider the following analysis.
Referring to FIG. 1, the time at which a known data sequence begins to be transmitted from the DUT is normally deterministic, and can be expressed as a number N of bit periods T, plus a phase offset, φ, as shown in Eq. 1
                              t          s                =                  NT          +                                    ϕ              ⁢                                                          ⁢              T                                      2              ⁢              π                                                          (                  eq          .                                          ⁢          1                )            
At low speeds, it is taken for granted that N never changes. More importantly, the deviation between the best and worst case φ is less then half a bit period. In that case, the strobe time is fixed between best and worst case, guaranteeing that the device's behavior will be observed at the proper time.
As frequency increases, the bit period is smaller than the maximum deviation of φ so there is no single fixed strobe time that will not reject good DUTs. In addition to this dilemma, serializer/deserializer circuits (SERDES) may be included on DUTs as functional blocks and there could be added variation on the phase depending on the status of the divided-by-N counter of the SERDES (where N is the ratio of the parallel to serial conversion).
Some prior systems use a search test built into some ATEs. In this test method the functional test is run multiple times until the correct strobe location if found, as shown in FIG. 2. It is mainly used for characterization because it is very time consuming, especially for devices that have a long PLL lock time.
A second solution uses an external time measurement unit (TMU) and a special pattern to find the strobe time.
The first method is mainly used for characterization and debugging. Use in production test was abandoned long ago and is no longer useful to at-speed testing because: (a) This solution requires the functional test to be run in every iteration of the loop. Depending on the strobe time search depth, many passes are typically required, resulting in a long total test time; and (b) This method applies PER PIN. Given that the time of (a) is tolerable (which it is not in some cases), the search must be done for every high speed pin being tested. Multiply the time of (a) by the number of pins and it becomes clear that this solution is quite limited and not at all applicable to, for example, devices with wide, high speed busses.
The second method is sometimes used in high-speed IC production testing. It's disadvantages are: (a) The data pattern from the device is limited to a train of 0's followed by a pulse. There may be are variants to this restriction but in general the number of possible patterns is limited; (b) Test time can be 100 ms or more per measurement per pin; (c) The test method is not easily scalable to wide busses.
This measurement cannot be used for devices with multiple high speed outputs because: (a) The TMU can only measure one pin at a time. To scale means to measure pins sequentially, which increases test time, or to use multiple TMU's, a solution that becomes physically and financially cumbersome with increasing bus width; and (b) Some devices do not function properly without a specific data pattern (e.g. a valid oc48 frame). It is not possible to test such a device because the pattern requirements for the test.